Trench DMOS device with reduced gate resistance and manufacturing method thereof

ABSTRACT

A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a National Phase filing under 35 U.S.C. §371 ofPCT/CN2013/091154 filed on Dec. 31, 2013, which claims priority toChinese Patent Application Serial No. 201310014452.0 tiled on Jan. 15,2013 the entire contents of which are hereby incorporated by referencein their entireties.

FIELD OF THE INVENTION

The present invention relates to a DMOS transistor, and moreparticularly, relates to a trench-type DMOS device and a manufacturingmethod thereof.

REARGROUND OF THE INVENTION

DMOS (Double-diffused MOS) transistor is a type of MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor), and employs twodiffusion steps in sequence which are aligned on the same edge to form agroove channel region of the transistor. Generally, DMOS transistor is adevice which works under a high voltage and a high current, serving asan independent transistor/unit in a power integrated circuit. DMOStransistor can provide a high current for each cell area which has a lowforward voltage drop.

The typical independent DMOS transistor structure includes two or morethan two single DMOS transistor units which are parallel manufactured.The single DMOS transistors share a common drain contact (substrate).The source electrodes thereof are short-cut by metal, and the gateelectrodes thereof are short-cut by poly-silicon. Therefore, even if theindependent DMOS circuit are constructed by small transistors array,when running, it serves as a single large transistor. For the singleindependent DMOS, when the transistor matrix are switched on via thegate electrode, it is desired to allow the electrical conductivity oneach cell area attaining a maximum value.

A specific DMOS transistor is the so-called trench-type DMOS transistor,wherein the groove channel is presented on an inner wall of the trenchextending from the source electrode to the drain electrode, and the gateelectrode is formed within the trench. Compared with the vertical DMOStransistor structure, minor limited current flowing through the trenchwhich is aligned to the thinner oxide layer to form a straight line andis filled with poly-silicon are permitted, thus providing a relative lowspecific turn-on resistance value.

For DMOS device, the gate electrode resistance determines the outputcapability of the device. Generally, in order to obtain a large amountof the output current, it is required to reduce the gate electroderesistance value Rg as more as possible. Among the existing methods, anapproach is to increase the number of the trenches, so as to reduce theRg. However, in such approach, the optimization of the Rg is limited,and accompanying to the increasing of the trenches, not only the size ofthe device is increased, but also the manufacturing method thereof ismore complicated.

Therefore, how to reduce the gate electrode resistance value Rg hasalready become an issue drawing intensive concerns in the industry.

SUMMARY OF THE INVENTION

Accordingly, it is necessary to provide a trench-type DMOS device havingrelative low gate electrode resistance Rg, and a method of manufacturingthe DMOS device.

a substrate of a first conductive type, the substrate serving as acommon drain region;

an active region of a second conductive type formed on the substrate;

a first dielectric layer formed on the substrate, the first dielectriclayer defining a plurality of trenches extending from a surface of thefirst dielectric layer to an interior of the substrate, the plurality oftrenches including a first trench located in the active region and asecond trench located outside the active region, the first trench fluidcommunicating with the second trench;

conductive material filled in the plurality of trenches;

an oxide layer positioned between the conductive material and trenchwalls of the plurality of trenches;

a source electrode region located in the active region and adjacent tothe first trench;

a second dielectric layer covering the first dielectric layer and theplurality of trenches; and

a metallic layer covering the second dielectric layer, wherein themetallic layer includes a first electrode region and a second electroderegion insulated from each other, the first electrode region iselectrically connected to the source electrode region via a firstconductive pole which extends through the first dielectric layer and thesecond dielectric layer, thereby forming a source electrode, the secondelectrode region is electrically connected to the conductive materialvia a second conductive pole which extends through the second dielectriclayer, thereby forming a gate electrode.

According to one embodiment, a depth of the trench is greater than adepth of the active region.

According to one embodiment, the substrate is an N-type substrate, theactive region is P-type active region, and the source electrode regionis a heavily doped N-type region.

According to one embodiment, the trench-type DMOS device furtherincludes a heavily doped P-type region located at a bottom of the activeregion beneath of the source electrode region.

According to one embodiment, the conductive material is polycrystallinesilicon, the oxide layer is made of silicon oxide.

According to one embodiment, the first conductive pole and the secondconductive are made of tungsten.

According to one embodiment, the substrate further includes a pluralityof P-type voltage-dividing rings located around the active region.

According to one embodiment, further including an oxide layer located ona top of the conductive material in the trench, wherein the oxide layerinsolates the conductive material from the second dielectric layer.

According to one embodiment, the first dielectric layer includes a boronphosphorous silicate glass layer, and a silicon oxide layer preparedfrom ethyl silicate, which is laminated on the silicon oxide layer theboron phosphorous silicate glass layer.

A method of manufacturing above-described trench-type DMOS device,includes:

providing a substrate of a first conductive type, the substrate servingas a common drain electrode region;

doping the substrate to form an active region of a second conductivetype;

forming a first dielectric layer on the substrate, and etching the firstdielectric layer to form a plurality of trenches, the plurality oftrenches extending from a surface of the first dielectric layer to aninterior of the substrate, the plurality of trenches including a firsttrench located in the active region and a second trench located outsidethe active region, the first trench being fluid communicated with thesecond trench;

forming an oxide layer on trench wall of the trench, and filling theplurality of trenches with conductive material;

depositing a second dielectric layer on the first dielectric layer andsurfaces of the trenches, and etching the second dielectric layer toform a first conductive via extending through the second dielectriclayer and the first dielectric layer, until the first conductive viareaching the substrate, and forming a second conductive via extendingthrough the second dielectric layer, until the second conductive viareaching the second trench, the first conductive via being adjacent tothe first trench;

applying a heavily doping of the first conductive type to the activeregion via the first conductive via, thereby forming a source electroderegion, and filling the first conductive via and the conductive via withtungsten, thereby forming a first conductive pole and a secondconductive pole; and

depositing a metallic layer on the second dielectric layer, and etchingthe metallic layer to form a first electrode region and a secondelectrode insulated from each other, electrically connecting the firstelectrode region to the source electrode region via the first conductivepole, thereby forming a source electrode, electrically connecting thesecond electrode region to the conductive material in the second trenchvia the second conductive pole, thereby forming a gate electrode.

According to one embodiment, a depth of the trench is greater than adepth of the active region.

According to one embodiment, the substrate is an N-type substrate, theactive region is P-type active region, and the source electrode regionis a heavily doped N-type region.

According to one embodiment, prior to the filing the first conductivevia with tungsten, the method further includes: applying anion-implantation to a bottom of the active region via the firstconductive via to form a heavily doped P-type region, the heavily dopedP-type region being located beneath the source electrode region.

According to one embodiment, the conductive material is polycrystallinesilicon, the oxide layer is made of silicon oxide.

According to one embodiment, after the forming an active region, themethod further includes: forming a plurality of P-type voltage-dividingrings around the active region of the substrate.

According to one embodiment, after the filling the plurality of trencheswith conductive material, the method further includes: forming an oxidelayer on a top of the conductive material in the trench, the oxide layerinsolating the conductive material from the second dielectric layer.

In the forgoing trench-type DMOS device, the trenches which serve as themain gate electrode region extend from the surface of the firstdielectric layer to the substrate. Compared to the conventional trenchesmanufactured merely in the substrate, the trench of the presentinvention enables the gate electrode polycrystalline silicon to have arelative larger cross-sectional area, thus effectively reducing the gateelectrode resistance Rg. In addition, in the process of manufacturingthe device, the injection of the source electrode region is directlyconducted by virtue of conductive via, the step of photo-etching for thesource injection is omitted, thus simplying the manufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the present invention will become readilyapparent upon further review of the following specification anddrawings. In the drawings, like reference numerals designatecorresponding parts throughout the views. Moreover, components in thedrawings are not necessarily drawn to scale, the emphasis instead beingplaced upon clearly illustrating the principles of the presentdisclosure.

FIG. 1 is a schematically view of a trench-type DMOS device according toan embodiment;

FIG. 2 is a flowchart of a method of manufacturing a trench-type DMOSdevice, according to an embodiment;

FIGS. 3A through 3E are cross-sectional views of the devicecorresponding to above-described method.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention are described more fully hereinafter withreference to the accompanying drawings. The various embodiments of theinvention may, however, be embodied in many different forms and shouldnot be construed as limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure will be thoroughand complete, and will fully convey the scope of the invention to thoseskilled in the art.

In view of the problem in the prior art that it is difficult toeffectively reduce the gate electrode resistance Rg of the trench-typeDOMS device, it is necessary for the embodiment to provide a trench-typeDMOS device and a manufacturing method thereof.

FIG. 1 schematically shows a trench-type DMOS device according to anembodiment. As shown in FIG. 1, the DMOS device includes a substrate100. The substrate 100 has a first conductive type, which can be N-type,and can also be P-type, depending on the device's function. Theembodiment takes the first conductive type as N-type for example.Similar to other trench-type DMOS devices, the substrate 100 serves as acommon drain region of the device.

The DMOS device further includes an active region 102 formed within thesubstrate 100. The active region 102 is a second conductive type region,and is formed by doping impurities of second conductive type into thesubstrate 100 via ion-implantation technology. The second conductivetype is P-type, for example. Further, in order to improve the breakdownvoltage of the device, at the time of manufacturing the active region102, in the procedure of one step ion-implantation process, a pluralityof voltage-dividing rings 103 are generally manufactured on thesubstrate 100. The voltage-dividing rings 103 are distributed around theactive region 102, conducting a surface breakdown protection.

The DOMS device further includes a first dielectric layer 110 formed onthe substrate 100. The first dielectric layer 110 generally includes aboron phosphorous silicate glass (BPSG) layer 111 which is prepared fromchemical vapor deposition, and a silicon dioxide (TEOS) layer 112 whichis prepared from chemical vapor deposition based upon ethyl silicate.The BPSG layer 111 is formed on the substrate 100, and generally servesas a buffer layer between the surfaces of the dielectric and thesilicon, due to the high toughness of the material and the impuritiesabsorption character. The TEOS layer 112 is laminated upon BPSG layer111. Due to a high hardness of the material and a better insulationeffect, the TEOS layer 112 facilitates to a batch growth and serves as ahost material of the dielectric layer.

The first dielectric layer 110 defines a plurality of trenches. Suchtrenches extends from the surface of the first dielectric layer 110 toan interior of the substrate 110. The trenches includes at least onefirst trench 141 (three first trenches shown in the figures) and asecond trench 142 fluid communicating with the first trench 141. The atleast one first trench 141 is distributed in the active region 102, thesecond trench 141 is located outside the active region 102. The firsttrench 141 constitutes the main gate electrode of the DMOS device. Thesecond trench 142 leads the gate electrode out, such that the secondtrench 142 is made much more bigger. In addition, in order to facilitatemanufacturing the leading wire of the gate electrode, it is desired toform the second trench 142 outside the active region 102, therefore,avoiding the mutual interference with the source electrode leading wire.Furthermore, it is desired to produce the trench munch more deeper, suchas reaching 1.1 micrometer in depth, such depth is greater than that ofthe active region 102 (about 0.8 micrometer), which is conductive tocontrol the device by the gate electrode voltage.

The trenches are filled with conductive materials 143 to form the gateelectrode. The conductive material 143 is polycrystalline silicon ingeneral. In some special application occasions, the conductive material143 may be metals such as aluminum, copper and so on. Between theconductive material 143 and the trench wall of the trench, an oxidelayer 144 is provided. The oxide layer 144 is silicon oxide in general,serving as a gate-oxide. Further, on a top of the conductive material143 in the trench, an oxide layer 145 is further included, and insolatesthe conductive material 143 from a second dielectric layer 120 formed inthe following steps.

The DMOS device further includes a source electrode region 104 in theactive region 102 formed by ion-implantation. Generally, the sourceelectrode region 104 is a heavily doped N-type region, which is formedon an adjacent region of the first trench 141. Further, a P-type heavilydoped region 105 can be formed on a bottom of the active region 120beneath the source electrode region 104. The P-type heavily doped region105 is formed by ion-implantation technology, and is configured forimproving a surging impact resistance of the device in switchingtransient.

The DMOS device further includes a second dielectric layer 120 coveringthe first dielectric layer 110 and the plurality of trenches.

The DMOS device further includes a metallic layer 130 covering thesecond dielectric layer 120. The metallic layer 130 includes a firstelectrode region 131 and a second electrode region 132 insulated fromeach other. The first electrode region 131 is electrically connected tothe source electrode region 104 via a first conductive pole 151 whichextends through the first dielectric layer 110 and the second dielectriclayer 120, thereby forming the source electrode. The second electroderegion 132 is electrically connected to the conductive material 143 viaa second conductive pole 152 which extends through the second dielectriclayer 120, thereby forming the gate electrode. The conductive poles areformed by connecting lines between metallic layers, the conductivematerial thereof is tungsten.

The manufacturing method of above-described trench-type DMOS device isillustrated hereinafter.

Referring to FIG. 3A through FIG. 3E together with FIG. 2 accordingly.FIG. 2 is a flowchart of a method for manufacturing a trench-type DMOSdevice of the present invention. FIG. 3A-3E are cross-sectional views ofthe DMOS device corresponding to above-described method. As shown in thefigures, the manufacturing method of the present invention includessteps as follows:

S1: active region technology: the substrate of the first conductive typeis doped to form an active region of the second conductive type. Theprocess specifically includes:

S11: an N-type substrate 100 is provided, the substrate 100 may besilicon substrate for example, and serves as a common drain electroderegion. The N-type substrate 100 is oxidized to form an oxide layer onthe surface, the oxide layer conducts a buffer protection in thefollowing ion-implantation.

S12: windows for ion-implantation are manufactured by photo-etchingprocess. Above-described substrate is coated with a photo-resist layer101. An active region mask is employed to conduct an exposure anddevelop step on the photo-resist 101 to pattern the photo-resist,thereby exposing parts of the substrate which is to form the activeregion. In the step, the active region mask may include voltage-dividingring patterns distributed around the active region, such thatvoltage-dividing rings 20 can be manufactured on the substrate 100simultaneously.

S13: the patterned photo-resist is employed as a mask, and anion-implantation is applied to the substrate.

S14: the photo-resist is removed.

S15: the ion-implantation region is driven in to allow the doped ions todiffuse, thereby forming the active region 102. The voltage-dividingrings 103 can be formed simultaneously in the step, referring to FIG.3A.

S2: trench etching technology: the first dielectric layer 110 ismanufactured on above-described substrate, and the first dielectriclayer 110 is etched to form a plurality of trenches. The plurality oftrenches extends from the surface of the first dielectric layer 110 toan interior of the substrate 110. The plurality of trenches is dividedinto at least one first trench 141 distributed in the active region anda second trench 142 distributed in the non-active region. The processspecially includes:

S21: the oxide layer formed in step S11 for buffering ion-implantationis stripped.

S22: a first dielectric layer 110 is deposited on the substrate afterstripping. The first dialectic layer 110 can be divided into a BPSGlayer 111 and a TEOS layer 112. In other occasions, the first dielectriclayer 110 may be one layer or more than two layers.

S23: windows for etching trench are manufactured on the first dielectriclayer 110 by photo-etching process. Special details of the photo-etchingprocess can be seen in S12, and are not specially described hereby.

S24: the first dielectric layer 110 is etched via windows formed by stepS23, thereby forming trench patterns in the dielectric layer 110.

S25: residual photo-resist in the step S24 is removed, the trenchpattern on the first dielectric layer 110 is employed as a mask and thesilicon substrate is etched to produce trenches thereon, thusaccomplishing the etching of the overall trenches, referring to FIG. 3B.

S3: gate oxide and gate polycrystalline silicon technology: an oxidelayer 144 is formed on the trench wall of the trench, and the pluralityof trenches are filled with conductive material 143. Generally, theconductive material 143 is polycrystalline silicon. In some especialapplication occasions, the conductive material 143 may be metals such asaluminum, copper and so on. The conductive material 143 and the oxidelayer 144 constitutes the gate electrode of the device. Referring toFIG. 3C, it clearly shows that, in the embodiment, the overall gateelectrode trenches protrude out of the substrate and reach the firstdielectric layer 110. Compared to the traditional structure thatproducing the overall gate electrode trenches merely in the substrate,the gate electrode conductive material of the embodiment has a relativelarger cross-sectional area, therefore, the gate electrode resistancethereof can be effectively reduced. The process specifically includes:

S31: a sacrificial oxide layer is manufactured on the substrate afterstep S25;

S32: the sacrificial oxide layer is fully stripped by wet-etchingtechnology;

S33: gate-oxide technology: an oxide layer is manufactured within thetrench, in general, the oxide layer is silicon dioxide.

S34: polycrystalline silicon is deposited on above-described structureby polycrystalline silicon deposition process, until the polycrystallinesilicon covers the overall surface, causing the trench structure to besufficiently filled with conductive material 143.

S35: a polycrystalline silicon/silicon dioxide high selectivity dryetching technology is preformed to remove all of the polycrystallinesilicon exposed out of the trench structure, until the etching reachesthe silicon dioxide material on the surface of the trench, therebyforming a structure having a cross-sectional view as shown in FIG. 3C.

S4: conductive via technology: a second dielectric layer 120 isdeposited on the surface of the trenches and the first dielectric layer110, and the second dielectric layer 120 is etched to form a firstconductive via 153 and a second conductive via 154, the first conductivevia 153 extends through the second dielectric layer 120, and the firstdielectric layer 110, until the first conductive via 153 reaches thesubstrate 100. The second conductive via 154 extends through the seconddielectric layer 120, until the second trench 142. The first conductivevia 153 is located adjacent to the first trench 141, referring to FIG.3D.

The process specifically includes:

S41: the polycrystalline silicon is oxidized, an oxide layer 145 ismanufactured on a top of the conductive material 143 in the trenchopening.

S42: a second dielectric layer is deposited, a second dielectric layer120 is deposited on the surface of the trench and the first dielectriclayer 110.

S43: windows for etching conductive via are manufactured on the seconddielectric layer by photo-etching process. The detail of thephoto-etching process can also refer to step S12.

S44: the windows formed by step S43 is employed as a mask, and apolycrystalline silicon/silicon dioxide high selectivity dry etchingtechnology is applied to the second dielectric layer 120 and the firstdielectric layer 110, to produce a conductive via. In the step, on thevia adjacent to the second trench, when the above second dielectriclayer 120 is etched, because the polycrystalline silicon is exposed onthe bottom, the etching is approximately quitted at the bottom.

S45: redundant photo-resistant of step S43 is removed.

S5: source electrode region and conductive pole technology: a heavilydoping of the first conductive type is applied to the active region 102via the first conductive via 153, thereby forming the source electroderegion 104. All of the conductive via is filled with tungsten, therebyforming the first conductive pole 151 and the second conductive pole152, referring to FIG. 3E.

The process specifically includes:

S51: an N-type ion-implantation and a rapid thermal annealing areapplied to the silicon substrate 100 via the first conductive via 153 toform an N--type heavily doped region, i.e. the source electrode region104.

S52: the second dielectric layer 120 is employed as a mask, and ansilicon etching is applied to the surface of the substrate 100corresponding to the first conductive via 153, to extend the firstconductive via 153 into the substrate 100, and extend the secondconductive via 154 into the second trench, Further, an ion-implantationmay be applied to the bottom of the active region 102 via the firstconductive via 153, thereby forming a heavily doped P-type region 105.The heavily doped P-type region 105 is formed below the source electroderegion 104, configured for improving a surging impact resistance of thedevice in switching transient.

S53: a titanium layer, or titanium oxide layer is deposited on thesubstrate after the step S52, serving as an conductive pole bufferlayer.

S54: all of the conductive via are filled with tungsten to formconductive poles. Thereafter, a chemical-mechanical polishing isperformed to remove the tungsten outside the holes.

S6: metallic layer technology: a metallic layer 130 is deposited on thesecond dielectric layer 120, and is etched to form a first electroderegion 131 and a second electrode 132 insulated from each other. Thefirst electrode region 131 is electrically connected to the sourceelectrode region 104 via the first conductive pole 151, thereby formingthe source electrode. The second electrode region 132 is electricallyconnected to the conductive material in the second trench via the secondconductive pole 152, thereby forming the gate electrode. Hence, thetrench-type DMOS device as shown in FIG. 1 is obtained.

The process specifically includes:

S61: a metal deposition is applied to the surface of the substrate afterstep S54, the metal may be Al, for example.

S62: windows for producing the first electrode region 131 and the secondelectrode 132 are formed on the surface of above-described metal, byphoto-etching technology. Special details of the photo-etching processcan be seen in step S12.

S63: the metal is etched via the windows formed by step S62 to form thefirst electrode region 131 and the second electrode 132, and then theredundant photo-resist is removed

S64: finally, an alloying technology is performed.

It is should be noted that, the semiconductor technology adopted by themanufacturing method of the present invention, such as ion-implantationtechnology, or deposition technology of the layers, are conventionalmethod at present. Therefore, specially illustration is not presentedhereby. However, one skilled in the art can implement according to themethod mentioned in the present invention, and as a conventional method,the technologies mentioned by the method above-described can be replacedby other technology having a same purpose but via different means.

With regard to the present invention, the advantages mainly depend upon:

First: the trenches which serves as the main gate electrode regionextends from the surface of the first dielectric layer to the substrate,compared to the existing trenches manufactured merely in the substrate,the trench of the present invention enables the gate electrodepolycrystalline silicon to have a relative larger cross-sectional area,and therefore, effectively reducing the gate electrode resistance Rg.

Second: in the process of manufacturing above-described device, thesubstrate is covered by the dielectric layer prior to etch the trenches,thus the original source electrode injection technology is therebyeliminated, instead, the source injection technology and the conductivevia is conducted in one photo-etching step, reducing one step ofphoto-etching, thus simply the whole technology.

Although the present invention is illustrated and described herein withreference to specific embodiments, the present invention is not intendedto be limited to the details shown. Rather, various modifications may bemade in the details within the scope and range of equivalents of theclaims and without departing from the present invention.

What is claimed is:
 1. A trench-type DMOS device, comprising: asubstrate of a first conductive type, the substrate serving as a commondrain region; an active region of a second conductive type formed on thesubstrate; a first dielectric layer formed on the substrate, the firstdielectric layer defining a plurality of trenches extending from asurface of the first dielectric layer to an interior of the substrate,the plurality of trenches comprising a first trench located in theactive region and a second trench located outside the active region, thefirst trench being fluid communicated with the second trench; conductivematerial filled in the plurality of trenches; an oxide layer positionedbetween the conductive material and trench walls of the plurality oftrenches; a source electrode region located in the active region andadjacent to the first trench; a second dielectric layer covering thefirst dielectric layer and the plurality of trenches; and a metalliclayer covering the second dielectric layer, wherein the metallic layercomprises a first electrode region and a second electrode regioninsulated from each other, the first electrode region is electricallyconnected to the source electrode region via a first conductive polewhich extends through the first dielectric layer and the seconddielectric layer, thereby forming a source electrode, the secondelectrode region is electrically connected to the conductive materialvia a second conductive pole which extends through the second dielectriclayer, thereby forming a gate electrode.
 2. The trench-type DMOS deviceaccording to claim 1, wherein a depth of the trench is greater than adepth of the active region.
 3. The trench-type DMOS device according toclaim 1, wherein the substrate is an N-type substrate, the active regionis P-type active region, and the source electrode region is a heavilydoped N-type region.
 4. The trench-type DMOS device according to claim3, further comprising a heavily doped P-type region located at a bottomof the active region beneath the source electrode region.
 5. Thetrench-type DMOS device according to claim 1, wherein the conductivematerial is polycrystalline silicon, the oxide layer is made of siliconoxide.
 6. The trench-type DMOS device according to claim 1, wherein thefirst conductive pole and the second conductive pole are made oftungsten.
 7. The trench-type DMOS device according to claim 1, whereinthe substrate further comprises a plurality of P-type voltage-dividingrings located around the active region.
 8. The trench-type DMOS deviceaccording to claim 1, further comprising an oxide layer located on a topof the conductive material in the trench, wherein the oxide layerinsolates the conductive material from the second dielectric layer. 9.The trench-type DMOS device according to claim 1, wherein the firstdielectric layer comprises a boron phosphorous silicate glass layer, anda silicon oxide layer prepared from ethyl silicate, which is laminatedon the boron phosphorous silicate glass layer.
 10. A method ofmanufacturing a trench-type DMOS device, comprising: providing asubstrate of a first conductive type, the substrate serving as a commondrain electrode region; doping the substrate to form an active region ofa second conductive type; forming a first dielectric layer on thesubstrate, and etching the first dielectric layer to from a plurality oftrenches, the plurality of trenches extending from a surface of thefirst dielectric layer to an interior of the substrate, the plurality oftrenches comprising a first trench located in the active region and asecond trench located outside the active region, the first trench beingfluid communicated with the second trench; forming an oxide layer on atrench wall of the trench, and filling the plurality of trenches withconductive material; depositing a second dielectric layer on the firstdielectric layer and surfaces of the trenches, and etching the seconddielectric layer to form a first conductive via extending through thesecond dielectric layer and the first dielectric layer, until the firstconductive via reaching the substrate, and forming a second conductivevia extending through the second dielectric layer, until the secondconductive via reaching the second trench, the first conductive viabeing adjacent to the first trench; applying a heavily doping of thefirst conductive type to the active region via the first conductive via,thereby forming a source electrode region, and filling the firstconductive via and the conductive via with tungsten, thereby forming afirst conductive pole and a second conductive pole; and depositing ametallic layer on the second dielectric layer, and etching the metalliclayer to form a first electrode region and a second electrode insulatedfrom each other, electrically connecting the first electrode region tothe source electrode region via the first conductive pole, therebyforming a source electrode, electrically connecting the second electroderegion to the conductive material in the second trench via the secondconductive pole, thereby forming a gate electrode.
 11. The manufacturingmethod according to claim 10, wherein a depth of the trench is greaterthan a depth of the active region.
 12. The manufacturing methodaccording to claim 10, wherein the substrate is an N-type substrate, theactive region is P-type active region, and the source electrode regionis a heavily doped N-type region.
 13. The manufacturing method accordingto claim 12, wherein prior to the filing the first conductive via withtungsten, the method further comprises: applying an ion-implantation toa bottom of the active region via the first conductive via to form aheavily doped P-type region, the heavily doped P-type region beinglocated beneath the source electrode region.
 14. The manufacturingmethod according to claim 10, wherein the conductive material ispolycrystalline silicon, and the oxide layer is made of silicon oxide.15. The manufacturing method according to claim 10, wherein after theforming an active region, the method further comprises: forming aplurality of P-type voltage-dividing rings around the active region ofthe substrate.
 16. The manufacturing method according to claim 10,wherein after the filling the plurality of trenches with conductivematerial, the method further comprises: forming an oxide layer on a topof the conductive material in the trench, the oxide layer insolating theconductive material from the second dielectric layer.